August 1997
CS202: COMPUTER ARCHITECTURE AND DATA COMMUNICATION

QUESTION 5

Total Marks: 20 Marks

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SUGGESTED SOLUTIONS
Solutions and allocated marks are indicated in green.
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5. (a) Identify and describe any four aspects of I/O behavior within an operating system. [8]
Award up to two marks for each of four aspects, [1]
for the function, [1]
for the explanation, [1]
Examples include
control and timing co-ordinate flow of traffic, sharing of internal resources.
CPU communication accept commands, report status, exchange data
device communication communicate with external device - commands, status, data
error detection detect errors and report to CPU
data buffering because CPU, memory, and external device have different transfer rates
(b) Give four reasons for the occurrence of an I/O interrupt. [4]
i/o transfer request, [1]
i/o transfer completion, [1]
device error, [1]
software error [1]
(c) Describe in detail the tasks performed by the operating system when an I/O interrupt occurs. [8]
The following things must be done by the OS when an interrupt is generated:
1. The state of the program in operation when the interrupt was generated and the location of the next instruction in memory must be saved. Then the program can be re-entered when the interrupt service routine is finished. The state of the program includes saving the PSW and necessary register contents. [2]
2. The lower level interrupts are disabled so that the ISR is not interrupted during execution. [1]
3. The device that generated the interrupt must be identified. For this purpose we can use the following techniques: [1]
software poll: Where each device is polled in a particular sequence to find out the source of the interrupt
Daisy chain: This technique is more efficient than software poll, which uses a technique of hardware polling. The technique is also referred to as vectored interrupts.
4. CPU must jump to the program that will service the interrupt. Normally, the address of this ISR is fixed and known to the hardware and for other cases the address is provided by the device itself. [2]
5. When the interrupt is serviced, all lower level interrupts will be enabled so that the lower priority devices can get service from the CPU. [2]
6. The state of the interrupts must be restored before returning to the interrupt program. [2]
7. The interrupted program continues to execute. [1]
[Max 8 marks]