April 2000 QUESTION 4 Total Marks: 15 Marks |
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SUGGESTED SOLUTIONS |
(a) Describe two ways of using an
n-bit two’s-complement parallel adder to perform n-bit subtraction. [3
marks]
(b) Design a circuit
to perform addition and subtraction of 3-bit two’s-complement numbers.
Used XOR gates, and have a control input A/S’. Label your circuit
design clearly. [4 marks]
(1 mark for chaining together the full adders, 1 mark for connecting the B inputs via XOR gates, 1 mark for correctly connecting the A/S’ control to the XOR gates and the carry-in; 1 mark for labeling and clarity.) [4 marks]
(c) Redesign the above
circuit to use XNOR gates instead of XOR gates. [4 marks]
(1 mark for chaining together the full adder, 1 mark for connecting the B inputs via XNOR gates, 1 mark for correctly connecting the A/S’ control to the XNOR gates and the carry-in; 1 mark for labeling and clarity.) [4 marks]
(d) Explain how to detect overflow in addition and subtraction of two’s-complement numbers. In each, give an expression characterizing overflow in terms of the signs SA, SB of the arguments, the sign SC of the result, and the carry out C. [4 marks] For addition, there is an overflow when the two arguments have the same sign and the sum has the opposite sign (1 mark). Overflow is thus characterized by SASBS’C + S’AS’BSC (1 mark). For subtraction, there is an overflow when the two arguments have different signs and the carry out is different from the sign of the difference (1 mark). Overflow is thus characterized by (SAS’B + S’ASB)(SCC’ + S’CC) (1mark). [4 marks] |