| (a) | With the aid of a diagram, show how the fetch-execute cycle incorporates a check for interrupts. | [10] |
| Award marks for the features
indicated. Allow credit for alternative valid answers.
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| (b) | An instruction such as LOAD M loads the data at the address M into the accumulator. Using a diagram, show how many memory reads are needed to fetch the instruction, given that both the opcode field and the main memory are 1 byte wide. The starting address (program counter) is FEDC and the instruction is LOAD A114 | [6] |
| Award one mark for showing the
PC loaded into the MAR, one mark for showing the MBR loaded into the IR. Award two marks
for showing the rolees of the buses, and one mark for showing the memory adddresses.
Alternative valid answers should receive full credit.
Three memory reads are required (1 mark).
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| (c) | The bus connects a number of different devices. Describe (with source and destination) two types of transfer that an interconnection bus structure must support. | [3] |
| Memory to CPU: the CPU
reads an instruction or a unit of data from memory (1 mark). CPU to Memory: the CPU writes a unit of data to memory (1 mark). I/O to CPU: the CPU reads data from an I/O device via an I/O module (1 mark). I/O to or from Memory: an I/O module is allowed to exchange data directly with memory going through the CPU, using direct memory access (DMA) (1 mark).
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| (d) | A computer system has a 128-bit instruction word and uses a 3-address format. There are 155 different general-purpose registers available. Assume that the use of any of these registers is required in a particular instruction - i.e. the appropriate register must be specified in the instruction word as a special field. If there are 200 different opcodes/instructions available for the system, what instruction format is needed? Show how you calculate your answer. | [5] |
| opcode field: must
allow allow 27 < 200 < 28 opcodes; therefore 8 bits (1 mark). register field: must allow 27 < 155 < 28 registers; therefore 8 bits (1 mark). operand field: divide remaining bits equally: (128 - (8 + 8))/3 = 37 bits each (2 marks) leaving one unused bit (1 mark). Allow credit for alternative methods of working (if correct). Allow sequential marks. |
