| A universal J-K flip-flop has two
synchronous (clocked) inputs J and K, two asynchronous inputs S and R, and a clock input
CLK.
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| (a) | When R = 0 and S = 0, the flip-flop
behaves exactly as an simple J-K flip-flop: it will hold, reset, set or toggle the output
depending upon the values of J and K when the clock reaches a negative edge. Using this
information, copy and complete the following characteristic table:
In a table,
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[6] |
| (b) | When R = 1 then the Q output of the
flip-flop is reset immediately to 0, whatever the value of the other inputs; the flip-flop
will change state without waiting for the next negative edge. When R = 0 and S = 1, the
output Q is set immediately to 1; again, the values of the other inputs do not matter.
Using this information, copy and complete the following table:
In the table, x indicates a don't care condition.
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[2] |
| (c) | Draw and fully label a circuit
diagram to show how 4 universal J-K flip-flops can be linked to produce a four-bit binary
asynchronous counter (a ripple up-counter). Your counter should have a shared reset
input which has the effect of setting all outputs to 0.
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[6] |
| (d) | Draw and fully label another circuit diagram to show how 4 universal J-K flip-flops can be linked to produce a four-bit binary asynchronous counter with a mod number of 10. This counter should return to 0000 after reaching the output 1001. Again, there is a shared reset input which - when set to 1 - will immediately return all outputs to 0. | [6] |
indicates that the clock reaches a
negative edge and x indicates a don't care condition.