August 1999
LD201 : LOGIC DESIGN

QUESTION 4

Total Marks: 20 Marks

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SUGGESTED SOLUTIONS
for Question 4
(a) Give the truth table for a half-adder.

 

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(b) Express the carry and sum terms of a half-adder using NAND and NOT operations only.

 

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(c) Hence draw a circuit for a half-adder using only NAND gates.

 

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(d) Show how to construct a full-adder using two half-adders and an OR gate.

 

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(e) Here is the truth table for a 4-to-1 multiplexor.

S1

 S0 B
0 0 A0
0 1 A1
1 0 A2
1 1 A3

(Thus, when S1 = 0 and S0 = 0, the value of B is the same as that of input A0, and so on.) Explain how such a multiplexor can be used to implement an arbitrary 3-input, 1-output circuit.

 

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(f) Hence show how to implement a full-adder using two 4-to-1 multiplexors.

 

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