August 1999
LD201 : LOGIC DESIGN

QUESTION 5

Total Marks: 20 Marks

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SUGGESTED SOLUTIONS
for Question 5
(a) Show how to construct an SR-latch from two NAND gates.

 

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(b) Distinguish between synchronous and asynchronous counters.

 

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(c) Design a 3-bit synchronous ring counter, using D flip-flops.

 

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(d) Design a 3-bit synchronous up counter, using T flip-flops.

 

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(e) Redesign your answer to part (d) as an asynchronous circuit.

 

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(f) If you has an up counter and a collection of ordinary logic gates, how would you construct a down counter?

 

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