| (a) |
Show how to construct an SR-latch from two
NAND gates. |
[1] |
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| (b) |
Distinguish between synchronous and
asynchronous counters. |
[2] |
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In a synchronous
counter, all the flip-flops are connected to a single clock; in an synchronous counter,
each flip-flop is triggered by the previous one. |
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| (c) |
Design a 3-bit synchronous ring counter, using
D flip-flops. |
[4] |
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| (d) |
Design a 3-bit synchronous up counter, using T
flip-flops. |
[6] |
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| (e) |
Redesign your answer to part (d) as an
asynchronous circuit. |
[5] |
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| (f) |
If you has an up counter and a collection of
ordinary logic gates, how would you construct a down counter? |
[2] |
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It suffices to negate
all the outputs. Therefore, one can send output through an inverter, or alternatively take
Q' rather than the Q outputs from the flip-flops. |
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